1. Field of the Invention
This invention relates to the field of pulse code modulation systems using dynamically modulated (DM) non-return-to-zero (NRZ) signals with self-clocking, and in particular, it relates to a circuit for selecting the correct clock pulses from a series of pulses that includes both the correct clock pulses and an interleaved set of pulses of the same frequency but timed midway between the correct clock pulses.
2. The Prior Art
When information is transmitted by means of a series of electrical pulses that can have either of two values which may be identified as 1 and 0, it is possible for the nature of the information to require that an indefinitely long series of pulses of one of the two values be transmitted. Thus, it might be necessary to transmit a long series of 0's or a long series of 1's. There is no difficulty in decoding such a signal if a clock pulse signal is also transmitted. However, the transmission of a clock pulse signal on a separate transmission medium or on a separate part of the same transmission medium as the information signal is considered to be wasteful of the medium or of the transmission equipment, and it has been found desirable to include the clock signal with the information signal in such a form that the clock signal can be extracted without adversely affecting the information signal.
U.S. Pat. No. 3,414,894 describes encoding and decoding apparatus in connection with a system that uses DM-NRZ pulses. The pulses have fixed, equal intervals which are referred to as bit cells. Even if the NRZ pulses were required to remain in one state for an indefinite interval of time, in which case the clock signal would normally be lost, the DM technique applied to steady NRZ pulses of one state results in DM pulses that swing back and forth between their two states at the basic repetition rate of the system. This regular change of the pulses from one state to the other would make available the clock signal that could be used in demodulating or decoding, the DM pulse signal.
However, the standard of DM requires that the state of a pulse during a given interval, or bit cell, be changed at the center of that bit cell if the pulse being subjected to DM is a 1 and that the DM signal remain in the same state if the pulse being encoded is a 0, except that the DM signal must change from one state to the other at the beginning of a second successive 0 pulse and at the beginning of the subsequent successive 0 pulses.
The clock signal is usually derived from the DM pulse signal by generating pulses that are timed to coincide with the transitions of the DM pulse signal from one state to the other. The difficulty is that some of these transitions occur at the intersection between successive bit cells, in the case of multiple successive 0 pulses, and other intersections occur in the middle of bit cells, in the case of the DM pulse signals that represent 1's. Although there may be a long sequence of DM signals representing 0's or representing 1's, any usable information will require that the DM signal include both 0's and 1's. The encoding requirement previously stated means that each DM pulse will have a duration at least as long as a bit cell of the original NRZ pulse signal but may include one and one-half bit cells or even two bit cells. It is a unique feature of the encoding definition that the only occasion when the DM signal can include two bit cells is in the encoding of an NRZ pulse sequence 101. It is to be understood that the 101 sequence may occur by itself or as part of a much longer sequence.
It is an object of the present invention to make use of the unique characteristics of a DM signal having a duration of two bit cells to obtain information concerning the correct timing of clock pulses obtained from the DM signal.